(a) Field of the Invention
The invention relates to a chip data compressing test multiplexing circuit, particularly to a chip data compressing test multiplexing circuit for increasing testing throughput.
(b) Description of the Related Art
An integrate circuit (IC) is one of essential electronic elements for an information appliance because of its great functionality and compact size. In order to assure the functionality of a chip, the chip is required to pass comprehensive tests. Generally, the test method is to input a known testing signal into the circuit in the chip and acquire a feedback signal from the circuit of the chip to thereby determine whether the chip functions normally or not.
However, in order to correctly test a chip, the architecture of the chip testing circuit according to the prior art, for example one cycle IO compress 8 read circuit to test 8 signals at once, should have two pins only for testing and two interface circuits connecting to two probes of the chip testing system. Thus, the number of pins for testing is increased and thereby the cost of the chip testing circuit is also increased. If the chip testing rate is to be increased, the number of probes should be increased as well. It results in the increase of the whole production cost.